cystech electronics corp. spec. no. : c731n3 issued date : 2016.12.12 revised date : page no. : 1/9 mtb150n10n3 cystek product specification 100v n-channel enhancement mode mosfet mtb150n10n3 bv dss 100v i d @ t a =25 c, v gs =10v 1.9a features ? simple drive requirement ? small package outline ? pb-free lead plating and halogen-free package symbol outline mtb150n10n3 sot-23 ordering information device package shipping MTB150N10N3-0-T1-G sot-23 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel g gate s source d drain r dson @v gs =10v, i d =1.6a 128m (typ) r dson @v gs =4.5v, i d =1.3a 135m (typ) environment friendly grade : s for rohs compliant products, g for rohs d g s compliant packing spec, t1 : 3000 pcs / tape & reel,7? reel product rank, zero for no rank products product name
cystech electronics corp. spec. no. : c731n3 issued date : 2016.12.12 revised date : page no. : 2/9 mtb150n10n3 cystek product specification absolute maximum ratings (ta=25 c) parameter symbol limits unit drain-source voltage v ds 100 gate-source voltage v gs 20 v continuous drain current @ t a =25 c, v gs =10v (note 3) 1.9 continuous drain current @ t a =70 c, v gs =10v (note 3) i d 1.5 pulsed drain current (notes 1, 2) i dm 10 a maximum power dissipation@ t a =25 (note 3) 1.25 maximum power dissipation@ t a =70 (note 3) p d 0.8 w operating junction and storage temperature range tj ; tstg -55~+150 c note : 1. pulse width limited by maximum junction temperature. 2. pulse width 300 s, duty cycle 2%. 3. surface mounted on 1 in2 copper pad of fr-4 board; 270 c/w when mounted on minimum copper pad thermal performance parameter symbol limit unit thermal resistance, junction-to-ambient, max r ja 100 thermal resistance, junction-to-case, max r jc 50 c/w note : surface mounted on 1 in2 copper pad of fr-4 board; 270 c/w when mounted on minimum copper pad electrical characteristics (tj=25 c, unless otherwise noted) symbol min. typ. max. unit test conditions static bv dss 100 - - v gs =0v, i d =250 a v gs(th) 1.0 - 2.5 v v ds =v gs , i d =250 a i gss - - 10 na v gs = 20v, v ds =0v - - 1 v ds =100v, v gs =0v i dss - - 10 a v ds =100v, v gs =0v (tj=85 c) - 128 165 i d =1.6a, v gs =10v *r ds(on) - 135 190 m i d =1.3a, v gs =4.5v *g fs - 3.9 - s v ds =10v, i d =1a dynamic ciss - 262 - coss - 38 - crss - 20 - pf v ds =25v, v gs =0v, f=1mhz t d(on) - 8 - t r - 18.6 - t d(off) - 19.4 - t f - 17.6 - ns v ds =50v, i d =1a, v gs =4.5v, r g =6.8
cystech electronics corp. spec. no. : c731n3 issued date : 2016.12.12 revised date : page no. : 3/9 mtb150n10n3 cystek product specification qg - 7.4 - qgs - 1 - qgd - 2.5 - nc v ds =50v, i d =1.6a, v gs =4.5v rg - 3.4 - f=1mhz source-drain diode *i s - - 1.9 *i sm - - 10 a *v sd - 0.77 1.2 v v gs =0v, i s =1.1a *trr - 15.8 - ns *qrr - 10.9 - nc i f =1.1a, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2% recommended soldering footprint
cystech electronics corp. spec. no. : c731n3 issued date : 2016.12.12 revised date : page no. : 4/9 mtb150n10n3 cystek product specification typical characteristics typical output characteristics 0 1 2 3 4 5 6 7 8 9 10 012345 v ds , drain-source voltage(v) i d , drain current(a) 10v,9v,8v,7v,6v,5v,4v,3.5v,3v v gs =2.5v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 10 100 1000 0.001 0.01 0.1 1 10 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs = 10 v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 012345678910 i dr , reverse drain current(a) v sd , source-drain voltage(v) tj=25c tj=150c static drain-source on-state resistance vs gate-source voltage 0 20 40 60 80 100 120 140 160 180 200 024681 0 drain-source on-state resistance vs junction tempearture 0.4 0.8 1.2 1.6 2 2.4 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =1.6a r dson @tj=25c : 128m typ. v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =1.6a
cystech electronics corp. spec. no. : c731n3 issued date : 2016.12.12 revised date : page no. : 5/9 mtb150n10n3 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 10 100 1000 0 5 10 15 20 25 30 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -75 -50 -25 0 25 50 75 100 125 150 175 tj, junction temperature(c) v gs(th) , normalized threshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 0.001 0.01 0.1 1 10 i d , drain current(a) g fs , forward transfer admittance(s) v ds =10v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 048121620 qg, total gate charge(nc) v gs , gate-source voltage(v) i d =1.6a v ds =50v v ds =20v v ds =80v maximum safe operating area 0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 100ms 1ms 100 s r ds( on) limited t a =25c, tj=150, v gs =10v r ja =100c/w, single pulse maximum drain current vs junction temperature 0 0.5 1 1.5 2 2.5 25 50 75 100 125 150 175 tj, junction temperature(c) i d , maximum drain current(a) t a =25c, v gs =10v, r ja =100c/w
cystech electronics corp. spec. no. : c731n3 issued date : 2016.12.12 revised date : page no. : 6/9 mtb150n10n3 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 2 4 6 8 10 01234 5 single pulse power rating, junction to ambient (note on page 2) 0 1 2 3 4 5 6 7 8 9 10 0.01 0.1 1 10 100 pulse width(s) power (w) t j(max) =150c t a =25c r ja =100c/w v ds =10v v gs , gate-source voltage(v) i d , drain current (a) transient thermal response curves 0.001 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 1.e+02 1.e+03 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.01 0.02 0.05 0.1 0.2 d=0.5 1.r ja (t)=r(t)*r ja 2.duty factor, d=t 1 /t 2 3.t jm -t a =p dm *r ja (t) 4.r ja =100c/w
cystech electronics corp. spec. no. : c731n3 issued date : 2016.12.12 revised date : page no. : 7/9 mtb150n10n3 cystek product specification reel dimension carrier tape dimension
cystech electronics corp. spec. no. : c731n3 issued date : 2016.12.12 revised date : page no. : 8/9 mtb150n10n3 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds 183 c 60-150 seconds time maintained above: ? temperature (t l ) 217 c ? time (t l ) 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak 10-30 seconds 20-40 seconds temperature(tp) ramp down rate 6 c/second max. 6c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c731n3 issued date : 2016.12.12 revised date : page no. : 9/9 mtb150n10n3 cystek product specification sot-23 dimension *: typical inches marking: date code te h5nt xx device code style: pin 1.gate 2.source 3.drain 3-lead sot-23 plastic surface mounted package cystek package code: n3 millimeters inches millimeters dim min. max. min. max. dim min. max. min. max. a 0.1102 0.1204 2.80 3.04 j 0.0032 0.0079 0.08 0.20 b 0.0472 0.0669 1.20 1.70 k 0.0118 0.0266 0.30 0.67 c 0.0335 0.0512 0.89 1.30 l 0.0335 0.0453 0.85 1.15 d 0.0118 0.0197 0.30 0.50 s 0.0830 0.1161 2.10 2.95 g 0.0669 0.0910 1.70 2.30 v 0.0098 0.0256 0.25 0.65 h 0.0000 0.0040 0.00 0.10 l1 0.0118 0.0197 0.30 0.50 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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